Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications

Nanosheets are the revolutionary change to overcome limitations of FinFET. In this paper, temperature dependence 10 nm junctionless (JL) nanosheet FET performance on DC and analog/RF characteristics investigated for first time using extended source/drain with high-k gate stack. The detailed analysis like transfer (ID-VGS), output (ID-VDS), drain induced barrier lowering (DIBL), subthreshold swing (SS) ION/IOFF ratio evaluated from 200 K 350 K. We also analyzed effect ON-OFF metric (Q), dynamic power, power consumption. Furthermore, understand device various process parameters doping work function variations presented at 300 proposed exhibits good switching behavior IOFF reaching less than nA all temperatures. cutoff frequency (fT) is determined be in THz range Q ranges between 1.5 2.2 ?S-dec/mV temperatures LG nm. Moreover, scaling lengths (LG = 5 20 nm) presented. From simulation we notice that a JL sensitive variations. At extremely scaled lesser consumption, decreases increase temperature. Thus, demonstrates as strong potential contender low high applications nano-regime.